1. Field of the Invention
This invention relates to a peripheral memory interface controller having a high bandwidth and more particularly for such a peripheral memory interface controller for a large data processing system having many hundreds of peripheral units.
2. Description of the Prior Art
In large commercial data processing systems for use in financial institutions and other endeavors, the very size of this system is a result of the huge amounts of data which must be processed. This in turn entails provision of a large input/output system to transfer the data to and from the periphery of the system and main memory. In some earlier systems, a number of I/O processors were employed to handle such data transfers such as illustrated in the Bock et al U.S. Pat. No. 3,654,621. However, in this situation, provisions must be made for the synchronization or at least scheduling of the I/O processors so that they are not both working on the same job at the same time. Furthermore, such large data processing systems employ a number of central processors for the actual data processing and thus, there are a number of requestors in contention for access to the main memory system which in turn slows down the throughput of the system.
It is, therefore, preferable to have only one I/O system contending for access to main memory and to provide that I/O system with a large bandwidth and also other features which minimize memory accesses to as large a degree as possible.
A particular I/O system is disclosed in the Peacock et al application U.S. Ser. No. 926,588, filed Nov. 4, 1986 and assigned to the assignee of the present application. Among other things, this application and related applications are directed towards means for offloading control of the I/O operations from the operating systems of the data processing system, managing disk caches in main memory thereby reducing the number of disk accesses required, and initiating independent operations of various port adapters or bus drivers with automatic data transfer from various selected peripheral devices. The present invention is directed towards a memory interface controller which interfaces between this I/O periphery and main memory and serves to act as a cache itself so as to reduce the number of memory requests by the I/O and to receive such memory requests in a pipelined fashion so as to increase the bandwidth between main memory and the periphery.
It is then an object of the present invention to provide an improved interface controller for memory-periphery data transfers in a large data transfer system.
It is another object of the present invention to provide an improved memory interface controller which serves as a cache between the periphery and main memory so that many memory requests can be handled in the interface controller without an actual memory access being required.
It is still a further object of the present invention to provide an improved memory interface controller for a large data processing system which serves to receive multiple memory requests from the periphery of the system in a pipelined or overlapped fashion so as to provide better bandwidth for memory-periphery data transfer.